FPGA-based architectures have emerged as a versatile acceleration solution for a wide range of applications, supported by High-Level Synthesis (HLS) tools. For error-resilient workloads, the use of approximate logic components, such as imprecise multipliers and adders, can significantly improve resource utilization and energy efficiency. However, these components must be carefully composed to avoid excessive error accumulation and to ensure valid application outputs. This repository contains the experimental data and analysis scripts from a study on approximate multiplier and adder designs for multiply–accumulate (MAC) operations in HLS-based accelerators. The experiments evaluate component combinations that reduce power and area while effectively mitigating output errors in a Sobel filter accelerator. The results show that optimized approximate designs can improve the Power–Area Product (PAP) by 36–49% compared to a precise implementation, while maintaining acceptable output quality. The dataset includes LUT and flip-flop (FF) utilization and multiple error metrics, including MAE, EP, MSE, SSIM, PSNR, WCE, and bias. The repository also provides Python scripts for data visualization, statistical analysis, and CSV export of all results, supporting reproducibility and further research.